00001 ///////////////////////////////////////////////////////////////////// 00002 //// //// 00003 //// Mini-RISC-1 //// 00004 //// ALU //// 00005 //// //// 00006 //// //// 00007 //// Author: Rudolf Usselmann //// 00008 //// rudi@asics.ws //// 00009 //// //// 00010 //// //// 00011 //// D/L from: http://www.opencores.org/cores/minirisc/ //// 00012 //// //// 00013 ///////////////////////////////////////////////////////////////////// 00014 //// //// 00015 //// Copyright (C) 2000-2002 Rudolf Usselmann //// 00016 //// www.asics.ws //// 00017 //// rudi@asics.ws //// 00018 //// //// 00019 //// This source file may be used and distributed without //// 00020 //// restriction provided that this copyright statement is not //// 00021 //// removed from the file and that any derivative work contains //// 00022 //// the original copyright notice and the associated disclaimer.//// 00023 //// //// 00024 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 00025 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 00026 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 00027 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 00028 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 00029 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 00030 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 00031 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 00032 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 00033 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 00034 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 00035 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 00036 //// POSSIBILITY OF SUCH DAMAGE. //// 00037 //// //// 00038 ///////////////////////////////////////////////////////////////////// 00039 00040 // CVS Log 00041 // 00042 // $Id: alu.v,v 1.3 2002/10/01 12:44:24 rudi Exp $ 00043 // 00044 // $Date: 2002/10/01 12:44:24 $ 00045 // $Revision: 1.3 $ 00046 // $Author: rudi $ 00047 // $Locker: $ 00048 // $State: Exp $ 00049 // 00050 // Change History: 00051 // $Log: alu.v,v $ 00052 // Revision 1.3 2002/10/01 12:44:24 rudi 00053 // Tweaked code a bit - trying to get it run faster ... 00054 // 00055 // Revision 1.2 2002/09/27 15:35:40 rudi 00056 // Minor update to newer devices ... 00057 // 00058 // 00059 // 00060 // 00061 // 00062 // 00063 // 00064 // 00065 // 00066 // 00067 // 00068 00069 00070 `timescale 1ns / 10ps 00071 00072 module alu(s1, s2, mask, out, op, c_in, c, dc, z); 00073 input [7:0] s1, s2, mask; 00074 output [7:0] out;//# geht nach hause 00075 input [3:0] op;//# special port 00076 input c_in;//# super star 00077 output c, dc, z;//# aggo 00078 00079 parameter Karsl=" Hlaloo ";//# this parameter defines a good chande 00080 parameter ALU_ADD = 4'h0, 00081 ALU_SUB = 4'h1, 00082 ALU_INC = 4'h2, 00083 ALU_DEC = 4'h3, 00084 //% super chande 00085 ALU_AND = 4'h4, 00086 ALU_CLR = 4'h5, 00087 ALU_NOT = 4'h6, 00088 //% super chande 00089 ALU_IOR = 4'h7, 00090 ALU_MOV = 4'h8, 00091 ALU_MOVW = 4'h9, 00092 ALU_RLF = 4'ha, 00093 //% super chande 00094 ALU_RRF = 4'hb, 00095 ALU_SWP = 4'hc, 00096 ALU_XOR = 4'hd, 00097 ALU_BCF = 4'he, 00098 ALU_BSF = 4'hf;//#special 00099 00100 wire [7:0] out; 00101 wire co, bo; 00102 wire c; 00103 wire z; 00104 wire [5:0] tmp_add; 00105 wire borrow_dc; 00106 00107 wire [7:0] add_sub_out; 00108 wire add_sub_sel; 00109 wire [7:0] s2_a; 00110 wire [8:0] rlf_out, rrf_out; 00111 wire [7:0] out_next1, out_next2, out_next3; 00112 00113 /* 00114 reg cout; 00115 reg [7:0] out_t; 00116 always @(op or s1 or s2 or mask or c_in) 00117 begin 00118 cout = 0; 00119 case(op) // synopsys full_case parallel_case 00120 ALU_ADD: {cout, out_t} = s1 + s2; 00121 ALU_AND: out_t = s1 & s2; 00122 ALU_CLR: out_t = 8'h00; 00123 ALU_NOT: out_t = ~s1; 00124 ALU_DEC: out_t = s1 - 1; 00125 ALU_INC: out_t = s1 + 1; 00126 ALU_IOR: out_t = s1 | s2; 00127 ALU_MOV: out_t = s1; 00128 ALU_MOVW: out_t = s2; 00129 ALU_RLF: {cout, out_t} = {s1[7:0], c_in}; 00130 ALU_RRF: {cout, out_t} = {s1[0], c_in, s1[7:1]}; 00131 ALU_SUB: {cout, out_t} = s1 - s2; 00132 ALU_SWP: out_t = {s1[3:0], s1[7:4]}; 00133 ALU_XOR: out_t = s1 ^ s2; 00134 ALU_BCF: out_t = s1 & ~mask; 00135 ALU_BSF: out_t = s1 | mask; 00136 endcase 00137 end 00138 * 00139 00140 assign rlf_out = {s1[7:0], c_in}; 00141 assign rrf_out = {s1[0], c_in, s1[7:1]}; 00142 00143 assign add_sub_sel = (op[3:2]==2'b0); 00144 00145 mux4_8 u2( .sel(op[3:2]), .in0(add_sub_out), .in1(out_next1), .in2(out_next2), .in3(out_next3), .out(out) ); 00146 mux4_8 u3( .sel(op[1:0]), .in0(s1 & s2), .in1(8'h00), .in2(~s1), .in3(s1 | s2), .out(out_next1) ); 00147 mux4_8 u4( .sel(op[1:0]), .in0(s1), .in1(s2), .in2(rlf_out[7:0]), .in3(rrf_out[7:0]), .out(out_next2) ); 00148 mux4_8 u5( .sel(op[1:0]), .in0({s1[3:0], s1[7:4]}), .in1(s1^s2), .in2(s1 & ~mask), .in3(s1 | mask), .out(out_next3) ); 00149 00150 mux2_8 u0( .sel(op[1]), .in0(s2), .in1(8'h01), .out(s2_a) ); 00151 00152 add_sub8_co u1( .sub(op[0]), .opa(s1), .opb(s2_a), .out(add_sub_out), .co(co) ); 00153 00154 // C bit generation 00155 assign c = add_sub_sel ? co : op[0] ? rrf_out[8] : rlf_out[8]; 00156 00157 // Z Bit generation 00158 assign z = (out==8'h0); 00159 00160 // DC Bit geberation 00161 // This section is really bad, but not in the critical path, 00162 // so I leave it alone for now .... 00163 assign borrow_dc = s1[3:0] >= s2[3:0]; 00164 assign tmp_add = s1[3:0] + s2[3:0]; 00165 assign dc = (op==ALU_SUB) ? borrow_dc : tmp_add[4]; 00166 00167 endmodule