Processes | |
PROCESS_2 | ( clk ) |
Signals | |
address_to_the_hdlc1 | std_logic_vector ( 7 DOWNTO 0 ) |
byteenablen_to_the_hdlc1 | std_logic |
readn_to_the_hdlc1 | STD_LOGIC |
writen_to_the_hdlc1 | STD_LOGIC |
writedata_to_the_hdlc1 | STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) |
readdata_from_the_hdlc1 | STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) |
address_to_the_hdlc2 | std_logic_vector ( 7 DOWNTO 0 ) |
byteenablen_to_the_hdlc2 | std_logic |
readn_to_the_hdlc2 | STD_LOGIC |
writen_to_the_hdlc2 | STD_LOGIC |
writedata_to_the_hdlc2 | STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) |
readdata_from_the_hdlc2 | STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) |
in_port_to_the_keyboard_pio | STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) |
irq_from_the_hdlc1 | STD_LOGIC |
irq_from_the_hdlc2 | STD_LOGIC |
reset | STD_LOGIC |
off_chip_addr | STD_LOGIC_VECTOR ( 19 DOWNTO 0 ) |
select_to_the_hdlc1 | STD_LOGIC |
select_to_the_hdlc2 | STD_LOGIC |
kbd_clk_en | std_logic |
cnt | integer RANGE 0 TO 111110 |
led4 | std_logic |
led3 | std_logic |
led2 | std_logic |
led1 | std_logic |
Components | |
hdlc_interface | Entity <hdlc_interface> |
keyboard_decoder | |
nios |
PROCESS_2 | ( | clk ) |
hdlc_interface [Component] |
keyboard_decoder [Component] |
nios [Component] |
address_to_the_hdlc1 std_logic_vector ( 7 DOWNTO 0 ) [Signal] |
byteenablen_to_the_hdlc1 std_logic [Signal] |
readn_to_the_hdlc1 STD_LOGIC [Signal] |
writen_to_the_hdlc1 STD_LOGIC [Signal] |
writedata_to_the_hdlc1 STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) [Signal] |
readdata_from_the_hdlc1 STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) [Signal] |
address_to_the_hdlc2 std_logic_vector ( 7 DOWNTO 0 ) [Signal] |
byteenablen_to_the_hdlc2 std_logic [Signal] |
readn_to_the_hdlc2 STD_LOGIC [Signal] |
writen_to_the_hdlc2 STD_LOGIC [Signal] |
writedata_to_the_hdlc2 STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) [Signal] |
readdata_from_the_hdlc2 STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) [Signal] |
in_port_to_the_keyboard_pio STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) [Signal] |
irq_from_the_hdlc1 STD_LOGIC [Signal] |
irq_from_the_hdlc2 STD_LOGIC [Signal] |
reset STD_LOGIC [Signal] |
off_chip_addr STD_LOGIC_VECTOR ( 19 DOWNTO 0 ) [Signal] |
select_to_the_hdlc1 STD_LOGIC [Signal] |
select_to_the_hdlc2 STD_LOGIC [Signal] |
kbd_clk_en std_logic [Signal] |
cnt integer RANGE 0 TO 111110 [Signal] |
led4 std_logic [Signal] |
led3 std_logic [Signal] |
led2 std_logic [Signal] |
led1 std_logic [Signal] |
nios0 PORT [Port Map] |
kbd PORT [Port Map] |
hdlc1 PORT [Port Map] |
hdlc2 PORT [Port Map] |