Processes | |
ALWAYS_14 | ( clk ) |
ALWAYS_15 | ( clk ) |
ALWAYS_16 | ( clk ) |
clock divider super | |
ALWAYS_17 | ( clk ) |
ALWAYS_18 | ( clk ) |
clock divider | |
ALWAYS_19 | ( clk ) |
Basic Decode extracted directly from the instruction. | |
ALWAYS_20 | ( clk ) |
ALWAYS_21 | ( clk ) |
ALWAYS_22 | ( clk ) |
ALWAYS_23 | ( clk ) |
ALWAYS_24 | ( instr_0 ) |
ALWAYS_25 | ( clk ) |
ALWAYS_26 | ( instr_0 ) |
ALWAYS_27 | ( instr_0 ) |
ALWAYS_28 | ( clk ) |
ALWAYS_29 | ( clk ) |
ALWAYS_30 | ( clk ) |
ALWAYS_31 | ( clk ) |
ALWAYS_32 | ( clk ) |
ALWAYS_33 | ( clk ) |
ALWAYS_34 | ( clk ) |
ALWAYS_35 | ( clk ) |
ALWAYS_36 | ( clk ) |
ALWAYS_37 | ( clk ) |
ALWAYS_38 | ( clk ) |
ALWAYS_39 | ( instr_0 ) |
ALWAYS_40 | ( clk ) |
ALWAYS_41 | ( clk ) |
ALWAYS_42 | ( clk ) |
ALWAYS_43 | ( clk ) |
ALWAYS_44 | ( clk ) |
ALWAYS_45 | ( clk ) |
ALWAYS_46 | ( clk ) |
ALWAYS_47 | ( clk ) |
ALWAYS_48 | ( clk ) |
ALWAYS_49 | ( clk ) |
ALWAYS_50 | ( clk ) |
ALWAYS_51 | ( clk ) |
ALWAYS_52 | ( clk ) |
ALWAYS_53 | ( clk ) |
ALWAYS_54 | ( clk ) |
ALWAYS_55 | ( clk ) |
ALWAYS_56 | ( clk ) |
ALWAYS_57 | ( clk ) |
ALWAYS_58 | ( clk ) |
Ports | |
clk | |
rst_in | |
inst_addr | |
inst_data | |
portain | |
portbin | |
portcin | |
portaout | |
portbout | |
portcout | |
trisa | |
trisb | |
trisc | |
tcki | |
wdt_en | |
Inputs | |
clk | |
rst_in | |
inst_data | [ 11 : 0 ] |
portain | [ 7 : 0 ] |
portbin | [ 7 : 0 ] |
portcin | [ 7 : 0 ] |
tcki | |
wdt_en | |
Outputs | |
inst_addr | [ 10 : 0 ] |
portaout | [ 7 : 0 ] |
portbout | [ 7 : 0 ] |
portcout | [ 7 : 0 ] |
trisa | [ 7 : 0 ] |
trisb | [ 7 : 0 ] |
trisc | [ 7 : 0 ] |
Parameters | |
PC_RST_VECTOR | 11 ' h000 |
STAT_RST_VALUE | 8 ' h18 |
OPT_RST_VALUE | 8 ' h3f |
FSR_RST_VALUE | 7 ' h0 |
TRIS_RST_VALUE | 8 ' hff |
ALU_ADD | 4 ' h0 |
ALU_SUB | 4 ' h1 |
ALU_INC | 4 ' h2 |
ALU_DEC | 4 ' h3 |
ALU_AND | 4 ' h4 |
ALU_CLR | 4 ' h5 |
ALU_NOT | 4 ' h6 |
ALU_IOR | 4 ' h7 |
ALU_MOV | 4 ' h8 |
ALU_MOVW | 4 ' h9 |
ALU_RLF | 4 ' ha |
ALU_RRF | 4 ' hb |
ALU_SWP | 4 ' hc |
ALU_XOR | 4 ' hd |
ALU_BCF | 4 ' he |
ALU_BSF | 4 ' hf |
I_ADDWF | 12 ' b0001_11??_???? |
I_ANDWF | 12 ' b0001_01??_???? |
I_CLRF | 12 ' b0000_011?_???? |
I_CLRW | 12 ' b0000_0100_0000 |
I_COMF | 12 ' b0010_01??_???? |
I_DEC | 12 ' b0000_11??_???? |
I_DECFSZ | 12 ' b0010_11??_???? |
I_INCF | 12 ' b0010_10??_???? |
I_INCFSZ | 12 ' b0011_11??_???? |
I_IORWF | 12 ' b0001_00??_???? |
I_MOV | 12 ' b0010_00??_???? |
I_MOVWF | 12 ' b0000_001?_???? |
I_NOP | 12 ' b0000_0000_0000 |
I_RLF | 12 ' b0011_01??_???? |
I_RRF | 12 ' b0011_00??_???? |
I_SUBWF | 12 ' b0000_10??_???? |
I_SWAPF | 12 ' b0011_10??_???? |
I_XORWF | 12 ' b0001_10??_???? |
I_BCF | 12 ' b0100_????_???? |
I_BSF | 12 ' b0101_????_???? |
I_BTFSC | 12 ' b0110_????_???? |
I_BTFSS | 12 ' b0111_????_???? |
I_ANDLW | 12 ' b1110_????_???? |
I_CALL | 12 ' b1001_????_???? |
I_CLRWDT | 12 ' b0000_0000_0100 |
I_GOTO | 12 ' b101?_????_???? |
I_IORLW | 12 ' b1101_????_???? |
I_MOVLW | 12 ' b1100_????_???? |
I_OPTION | 12 ' b0000_0000_0010 |
I_RETLW | 12 ' b1000_????_???? |
I_SLEEP | 12 ' b0000_0000_0011 |
I_TRIS | 12 ' b0000_0000_0??? |
I_XORLW | 12 ' b1111_????_???? |
INDF_ADDR | 3 ' h0 |
TMR0_ADDR | 3 ' h1 |
PCL_ADDR | 3 ' h2 |
STAT_ADDR | 3 ' h3 |
FSR_ADDR | 3 ' h4 |
PORTA_ADDR | 3 ' h5 |
PORTB_ADDR | 3 ' h6 |
PORTC_ADDR | 3 ' h7 |
K_SEL | 2 ' b10 |
SFR_SEL | 2 ' b00 |
RF_SEL | 2 ' b01 |
STAT_WR_C | 3 ' b001 |
STAT_WR_DC | 3 ' b010 |
STAT_WR_Z | 3 ' b100 |
Registers | |
rst | |
instr_0 | [ 11 : 0 ] |
instr_1 | [ 11 : 0 ] |
rst_r1 | |
rst_r2 | |
valid_1 | |
mask | [ 7 : 0 ] |
sfr_rd_data | [ 7 : 0 ] |
alu_op | [ 3 : 0 ] |
src1_sel | |
src1_sel_ | [ 1 : 0 ] |
stat_bwe | [ 2 : 0 ] |
pc_skz | |
pc_skz_ | |
pc_bset | |
pc_bset_ | |
pc_bclr | |
pc_bclr_ | |
pc_call | |
pc_call_ | |
pc_goto | |
pc_goto_ | |
pc_retlw | |
pc_retlw_ | |
invalidate_0 | |
w_we_ | |
rf_we_ | |
sfr_we_ | |
tris_we_ | |
w_we | |
rf_we1 | |
rf_we2 | |
rf_we3 | |
opt_we | |
trisa_we | |
trisb_we | |
trisc_we | |
tmr0_we | |
pc_we | |
stat_we | |
fsr_we | |
porta_we | |
portb_we | |
portc_we | |
wdt_clr | |
inst_addr | [ 10 : 0 ] |
pc | [ 10 : 0 ] |
pc_r | [ 10 : 0 ] |
pc_r2 | [ 10 : 0 ] |
w | [ 7 : 0 ] |
status | [ 7 : 0 ] |
fsr | [ 6 : 0 ] |
tmr0 | [ 7 : 0 ] |
option | [ 5 : 0 ] |
trisa | [ 7 : 0 ] |
trisb | [ 7 : 0 ] |
trisc | [ 7 : 0 ] |
porta_r | [ 7 : 0 ] |
portb_r | [ 7 : 0 ] |
portc_r | [ 7 : 0 ] |
portaout | [ 7 : 0 ] |
portbout | [ 7 : 0 ] |
portcout | [ 7 : 0 ] |
instd_zero | |
w_we1 | |
w_we1_ | |
invalidate_1_r1 | |
invalidate_1_r2 | |
Components | |
u0 | Module register_file |
u3 | Module mux2_8 |
u4 | Module alu |
u21 | Module mux2_8 |
u31 | Module mux2_7 |
u5 | Module mux2_8 |
u6 | Module mux2_8 |
u7 | Module inc8 |
u8 | Module presclr_wdt |
u9 | Module mux2_11 |
u10 | Module mux2_11 |
u11 | Module mux2_11 |
u12 | Module mux2_11 |
u13 | Module inc11 |
u22 | Module mux8_1 |
u14 | Module sfifo4x11 |
Definition at line 71 of file risc_core.v.
ALWAYS_14 | ( | clk ) |
Definition at line 307 of file risc_core.v.
00307 always @(posedge clk) 00308 rst <= #1 rst_in; 00309 00310 //////////////////////////////////////////////////////////////////////// 00311 // Synchrounous Register File 00312 register_file
ALWAYS_15 | ( | clk ) |
Definition at line 325 of file risc_core.v.
00325 always @(posedge clk) 00326 instr_0 <= #1 inst_data; 00327 00328 //////////////////////////////////////////////////////////////////////// 00329 // Instr Decode & Read Logic 00330 //% clock divider super 00331 always
ALWAYS_16 | ( | clk ) |
ALWAYS_17 | ( | clk ) |
ALWAYS_18 | ( | clk ) |
ALWAYS_19 | ( | clk ) |
Basic Decode extracted directly from the instruction.
Definition at line 344 of file risc_core.v.
00344 always @(posedge clk) //# Basic Decode extracted directly from the instruction 00345 begin 00346 // Mask for bit modification instructions 00347 case(instr_0[7:5]) // synopsys full_case parallel_case 00348 0: mask <= #1 8'h01; 00349 1: mask <= #1 8'h02; 00350 2: mask <= #1 8'h04; 00351 3: mask <= #1 8'h08; 00352 4: mask <= #1 8'h10; 00353 5: mask <= #1 8'h20; 00354 6: mask <= #1 8'h40; 00355 7: mask <= #1 8'h80; 00356 endcase 00357 end
ALWAYS_20 | ( | clk ) |
Definition at line 359 of file risc_core.v.
00359 always @(posedge clk) 00360 pc_r <= #1 pc; // Previous version of PC to accomodate for pipeline
ALWAYS_21 | ( | clk ) |
Definition at line 362 of file risc_core.v.
00362 always @(posedge clk) // SFR Read Operands 00363 if(src1_sel_[1]) sfr_rd_data <= #1 instr_0[7:0]; 00364 else 00365 case(instr_0[2:0]) // synopsys full_case parallel_case 00366 1: sfr_rd_data <= #1 tmr0_next; 00367 2: sfr_rd_data <= #1 pc_r[7:0]; 00368 3: sfr_rd_data <= #1 status_next; 00369 4: sfr_rd_data <= #1 {1'b1, fsr_next}; 00370 5: sfr_rd_data <= #1 porta_r; 00371 6: sfr_rd_data <= #1 portb_r; 00372 7: sfr_rd_data <= #1 portc_r;
ALWAYS_22 | ( | clk ) |
Definition at line 412 of file risc_core.v.
00412 always @(posedge clk) 00413 instd_zero <= #1 !(|inst_data[4:0]);
ALWAYS_23 | ( | clk ) |
Definition at line 420 of file risc_core.v.
00420 always @(posedge clk) 00421 casex(instr_0) // synopsys full_case parallel_case 00422 // Byte Oriented RF Operations 00423 I_ADDWF: alu_op <= #1 ALU_ADD; // ADDWF 00424 I_ANDWF: alu_op <= #1 ALU_AND; // ANDWF 00425 I_CLRF: alu_op <= #1 ALU_CLR; // CLRF 00426 I_CLRW: alu_op <= #1 ALU_CLR; // CLRW 00427 I_COMF: alu_op <= #1 ALU_NOT; // COMF 00428 I_DEC: alu_op <= #1 ALU_DEC; // DEC 00429 I_DECFSZ: alu_op <= #1 ALU_DEC; // DECFSZ 00430 I_INCF: alu_op <= #1 ALU_INC; // INCF 00431 I_INCFSZ: alu_op <= #1 ALU_INC; // INCFSZ 00432 I_IORWF: alu_op <= #1 ALU_IOR; // IORWF 00433 I_MOV: alu_op <= #1 ALU_MOV; // MOV 00434 I_MOVWF: alu_op <= #1 ALU_MOVW; // MOVWF 00435 I_RLF: alu_op <= #1 ALU_RLF; // RLF 00436 I_RRF: alu_op <= #1 ALU_RRF; // RRF 00437 I_SUBWF: alu_op <= #1 ALU_SUB; // SUBWF 00438 I_SWAPF: alu_op <= #1 ALU_SWP; // SWAPF 00439 I_XORWF: alu_op <= #1 ALU_XOR; // XORWF 00440 // Bit Oriented RF Operations 00441 I_BCF: alu_op <= #1 ALU_BCF; // BCF 00442 I_BSF: alu_op <= #1 ALU_BSF; // BSF 00443 // Literal & Controll Operations 00444 I_ANDLW: alu_op <= #1 ALU_AND; // ANDLW 00445 I_IORLW: alu_op <= #1 ALU_IOR; // IORLW 00446 I_MOVLW: alu_op <= #1 ALU_MOV; // MOWLW 00447 I_RETLW: alu_op <= #1 ALU_MOV; // RETLW 00448 I_XORLW: alu_op <= #1 ALU_XOR; // XORLW
ALWAYS_24 | ( | instr_0 ) |
Definition at line 455 of file risc_core.v.
00455 always @(instr_0) 00456 casex(instr_0) // synopsys full_case parallel_case 00457 I_ANDLW: src1_sel_ = K_SEL; 00458 I_CALL: src1_sel_ = K_SEL; 00459 I_GOTO: src1_sel_ = K_SEL; 00460 I_IORLW: src1_sel_ = K_SEL; 00461 I_MOVLW: src1_sel_ = K_SEL; 00462 I_RETLW: src1_sel_ = K_SEL; 00463 I_XORLW: src1_sel_ = K_SEL; 00464 default: src1_sel_ = ( (instr_0[4:3]==2'h0) & (instr_0[2:0] != 3'h0 )) ? SFR_SEL : RF_SEL;
ALWAYS_25 | ( | clk ) |
ALWAYS_26 | ( | instr_0 ) |
Definition at line 477 of file risc_core.v.
00477 always @(instr_0) 00478 begin 00479 casex(instr_0) // synopsys full_case parallel_case 00480 I_ADDWF, I_ANDWF, I_COMF, I_DEC, 00481 I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, 00482 I_MOV, I_RLF, I_RRF, I_SUBWF, 00483 I_SWAPF, I_XORWF: // w or f 00484 w_we1_ = 1; 00485 default: w_we1_ = 0; 00486 endcase 00487 end
ALWAYS_27 | ( | instr_0 ) |
Definition at line 489 of file risc_core.v.
00489 always @(instr_0) 00490 begin 00491 w_we_ = 0; 00492 rf_we_ = 0; 00493 sfr_we_ = 0; 00494 tris_we_= 0; 00495 casex(instr_0) // synopsys full_case parallel_case 00496 00497 I_ADDWF, I_ANDWF, I_COMF, I_DEC, 00498 I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, 00499 I_MOV, I_RLF, I_RRF, I_SUBWF, 00500 I_SWAPF, I_XORWF: // w or f 00501 begin 00502 rf_we_ = instr_0[5] & (instr_0[4] | instr_0[3]); 00503 sfr_we_ = instr_0[5] & ~instr_0[4] & ~instr_0[3]; 00504 end 00505 00506 I_MOVWF, I_CLRF, I_BCF, I_BSF: // only f 00507 begin 00508 rf_we_ = instr_0[4] | instr_0[3]; 00509 sfr_we_ = ~instr_0[4] & ~instr_0[3]; 00510 end 00511 00512 I_CLRW, I_IORLW, I_MOVLW, 00513 I_ANDLW, I_RETLW, I_XORLW: w_we_ = 1; // only w 00514 I_TRIS: tris_we_ = 1; // trisa or trisb or trisc 00515 00516 endcase 00517 end
ALWAYS_28 | ( | clk ) |
ALWAYS_29 | ( | clk ) |
ALWAYS_30 | ( | clk ) |
ALWAYS_31 | ( | clk ) |
Definition at line 537 of file risc_core.v.
00537 always @(posedge clk) 00538 rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]);// register file write enable 2
ALWAYS_32 | ( | clk ) |
ALWAYS_33 | ( | clk ) |
ALWAYS_34 | ( | clk ) |
ALWAYS_35 | ( | clk ) |
Definition at line 551 of file risc_core.v.
00551 always @(posedge clk) 00552 trisa_we <= #1 tris_we_ & (instr_0[2:0] == PORTA_ADDR);
ALWAYS_36 | ( | clk ) |
Definition at line 554 of file risc_core.v.
00554 always @(posedge clk) 00555 trisb_we <= #1 tris_we_ & (instr_0[2:0] == PORTB_ADDR);
ALWAYS_37 | ( | clk ) |
Definition at line 557 of file risc_core.v.
00557 always @(posedge clk) 00558 trisc_we <= #1 tris_we_ & (instr_0[2:0] == PORTC_ADDR);
ALWAYS_38 | ( | clk ) |
Definition at line 560 of file risc_core.v.
00560 always @(posedge clk) 00561 begin 00562 // SFR registers 00563 tmr0_we <= #1 sfr_we_ & (instr_0[2:0] == TMR0_ADDR); 00564 pc_we <= #1 valid & pc_we_; 00565 stat_we <= #1 valid & sfr_we_ & (instr_0[2:0] == STAT_ADDR); 00566 fsr_we <= #1 valid & sfr_we_ & (instr_0[2:0] == FSR_ADDR); 00567 porta_we <= #1 sfr_we_ & (instr_0[2:0] == PORTA_ADDR); 00568 portb_we <= #1 sfr_we_ & (instr_0[2:0] == PORTB_ADDR); 00569 portc_we <= #1 sfr_we_ & (instr_0[2:0] == PORTC_ADDR); 00570 end
ALWAYS_39 | ( | instr_0 ) |
Definition at line 574 of file risc_core.v.
00574 always @(instr_0) 00575 begin 00576 pc_skz_ = 0; 00577 pc_bset_ = 0; 00578 pc_bclr_ = 0; 00579 pc_call_ = 0; 00580 pc_goto_ = 0; 00581 pc_retlw_ = 0; 00582 casex(instr_0) // synopsys full_case parallel_case 00583 // Byte Oriented RF Operations 00584 I_DECFSZ, 00585 I_INCFSZ: pc_skz_ = 1; 00586 // Bit Oriented RF Operations 00587 I_BTFSS: pc_bset_ = 1; 00588 I_BTFSC: pc_bclr_ = 1; 00589 // Literal & Controll Operations 00590 I_CALL: pc_call_ = 1; 00591 I_GOTO: pc_goto_ = 1; 00592 I_RETLW: pc_retlw_ = 1; 00593 endcase 00594 end
ALWAYS_40 | ( | clk ) |
Definition at line 596 of file risc_core.v.
00596 always @(posedge clk) 00597 begin 00598 pc_skz <= #1 valid & pc_skz_; 00599 pc_bset <= #1 valid & pc_bset_; 00600 pc_bclr <= #1 valid & pc_bclr_; 00601 pc_call <= #1 valid & pc_call_; 00602 pc_goto <= #1 valid & pc_goto_; 00603 pc_retlw <= #1 valid & pc_retlw_; 00604 end
ALWAYS_41 | ( | clk ) |
Definition at line 608 of file risc_core.v.
00608 always @(posedge clk) 00609 invalidate_0 <= #1 invalidate_0_;
ALWAYS_42 | ( | clk ) |
Definition at line 612 of file risc_core.v.
00612 always @(posedge clk) 00613 begin 00614 stat_bwe <= #1 0; 00615 if(valid) 00616 casex(instr_0) // synopsys full_case parallel_case 00617 // Byte Oriented RF Operations 00618 I_ADDWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; 00619 I_ANDWF: stat_bwe <= #1 STAT_WR_Z; 00620 I_CLRF: stat_bwe <= #1 STAT_WR_Z; 00621 I_CLRW: stat_bwe <= #1 STAT_WR_Z; 00622 I_COMF: stat_bwe <= #1 STAT_WR_Z; 00623 I_DEC: stat_bwe <= #1 STAT_WR_Z; 00624 I_INCF: stat_bwe <= #1 STAT_WR_Z; 00625 I_IORWF: stat_bwe <= #1 STAT_WR_Z; 00626 I_MOV: stat_bwe <= #1 STAT_WR_Z; 00627 I_RLF: stat_bwe <= #1 STAT_WR_C; 00628 I_RRF: stat_bwe <= #1 STAT_WR_C; 00629 I_SUBWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z; 00630 I_XORWF: stat_bwe <= #1 STAT_WR_Z; 00631 // Literal & Controll Operations 00632 I_ANDLW: stat_bwe <= #1 STAT_WR_Z; 00633 //I_CLRWDT: // Modifies TO & PD *** FIX ME *** 00634 I_IORLW: stat_bwe <= #1 STAT_WR_Z; 00635 //I_SLEEP: // Modifies TO & PD *** FIX ME *** 00636 I_XORLW: stat_bwe <= #1 STAT_WR_Z; 00637 endcase 00638 end
ALWAYS_43 | ( | clk ) |
Definition at line 690 of file risc_core.v.
00690 always @(posedge clk) 00691 if(rst) status <= #1 STAT_RST_VALUE; 00692 else status <= #1 status_next;
ALWAYS_44 | ( | clk ) |
Definition at line 698 of file risc_core.v.
00698 always @(posedge clk) 00699 if(rst) fsr <= #1 FSR_RST_VALUE; 00700 else fsr <= #1 fsr_next;
ALWAYS_45 | ( | clk ) |
ALWAYS_46 | ( | clk ) |
Definition at line 705 of file risc_core.v.
00705 always @(posedge clk) 00706 if(rst) trisa <= #1 TRIS_RST_VALUE; 00707 else 00708 if(trisa_we & valid_1) trisa <= #1 w;
ALWAYS_47 | ( | clk ) |
Definition at line 710 of file risc_core.v.
00710 always @(posedge clk) 00711 if(rst) trisb <= #1 TRIS_RST_VALUE; 00712 else 00713 if(trisb_we & valid_1) trisb <= #1 w;
ALWAYS_48 | ( | clk ) |
Definition at line 715 of file risc_core.v.
00715 always @(posedge clk) 00716 if(rst) trisc <= #1 TRIS_RST_VALUE; 00717 else 00718 if(trisc_we & valid_1) trisc <= #1 w;
ALWAYS_49 | ( | clk ) |
Definition at line 720 of file risc_core.v.
00720 always @(posedge clk) 00721 if(rst) option <= #1 OPT_RST_VALUE; 00722 else 00723 if(opt_we & valid_1) option <= #1 w[5:0];
ALWAYS_50 | ( | clk ) |
ALWAYS_51 | ( | clk ) |
ALWAYS_52 | ( | clk ) |
ALWAYS_53 | ( | clk ) |
ALWAYS_54 | ( | clk ) |
ALWAYS_55 | ( | clk ) |
ALWAYS_56 | ( | clk ) |
Definition at line 785 of file risc_core.v.
00785 always @(posedge clk) 00786 if(rst) inst_addr <= #1 PC_RST_VECTOR; 00787 else inst_addr <= #1 pc_next;
ALWAYS_57 | ( | clk ) |
Definition at line 789 of file risc_core.v.
00789 always @(posedge clk) 00790 if(rst) pc <= #1 PC_RST_VECTOR; 00791 else pc <= #1 pc_next;
ALWAYS_58 | ( | clk ) |
Definition at line 830 of file risc_core.v.
00830 always @(posedge clk) 00831 begin 00832 invalidate_1_r1 <= #1 (invalidate_0 & valid_1) | invalidate_1_r2; 00833 invalidate_1_r2 <= #1 (invalidate_0 & valid_1); 00834 end
clk [Ports] |
Definition at line 72 of file risc_core.v.
rst_in [Ports] |
Definition at line 73 of file risc_core.v.
inst_addr [Ports] |
Definition at line 75 of file risc_core.v.
inst_data [Ports] |
Definition at line 76 of file risc_core.v.
portain [Ports] |
Definition at line 78 of file risc_core.v.
portbin [Ports] |
Definition at line 79 of file risc_core.v.
portcin [Ports] |
Definition at line 80 of file risc_core.v.
portaout [Ports] |
Definition at line 82 of file risc_core.v.
portbout [Ports] |
Definition at line 83 of file risc_core.v.
portcout [Ports] |
Definition at line 84 of file risc_core.v.
trisa [Ports] |
Definition at line 86 of file risc_core.v.
trisb [Ports] |
Definition at line 87 of file risc_core.v.
trisc [Ports] |
Definition at line 88 of file risc_core.v.
tcki [Ports] |
Definition at line 90 of file risc_core.v.
wdt_en [Ports] |
Definition at line 91 of file risc_core.v.
clk [Inputs] |
Definition at line 94 of file risc_core.v.
rst_in [Inputs] |
Definition at line 95 of file risc_core.v.
inst_addr [ 10 : 0 ] [Outputs] |
Definition at line 98 of file risc_core.v.
inst_data [ 11 : 0 ] [Inputs] |
Definition at line 99 of file risc_core.v.
portain [ 7 : 0 ] [Inputs] |
Definition at line 102 of file risc_core.v.
portbin [ 7 : 0 ] [Inputs] |
Definition at line 103 of file risc_core.v.
portcin [ 7 : 0 ] [Inputs] |
Definition at line 104 of file risc_core.v.
portaout [ 7 : 0 ] [Outputs] |
Definition at line 106 of file risc_core.v.
portbout [ 7 : 0 ] [Outputs] |
Definition at line 107 of file risc_core.v.
portcout [ 7 : 0 ] [Outputs] |
Definition at line 108 of file risc_core.v.
trisa [ 7 : 0 ] [Outputs] |
Definition at line 110 of file risc_core.v.
trisb [ 7 : 0 ] [Outputs] |
Definition at line 111 of file risc_core.v.
trisc [ 7 : 0 ] [Outputs] |
Definition at line 112 of file risc_core.v.
tcki [Inputs] |
Definition at line 114 of file risc_core.v.
wdt_en [Inputs] |
Definition at line 115 of file risc_core.v.
PC_RST_VECTOR [Parameters] |
Definition at line 119 of file risc_core.v.
STAT_RST_VALUE [Parameters] |
Definition at line 119 of file risc_core.v.
OPT_RST_VALUE [Parameters] |
Definition at line 119 of file risc_core.v.
FSR_RST_VALUE [Parameters] |
Definition at line 119 of file risc_core.v.
TRIS_RST_VALUE [Parameters] |
Definition at line 119 of file risc_core.v.
ALU_ADD [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_SUB [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_INC [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_DEC [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_AND [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_CLR [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_NOT [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_IOR [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_MOV [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_MOVW [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_RLF [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_RRF [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_SWP [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_XOR [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_BCF [Parameters] |
Definition at line 125 of file risc_core.v.
ALU_BSF [Parameters] |
Definition at line 125 of file risc_core.v.
I_ADDWF [Parameters] |
Definition at line 143 of file risc_core.v.
I_ANDWF [Parameters] |
Definition at line 143 of file risc_core.v.
I_CLRF [Parameters] |
Definition at line 143 of file risc_core.v.
I_CLRW [Parameters] |
Definition at line 143 of file risc_core.v.
I_COMF [Parameters] |
Definition at line 143 of file risc_core.v.
I_DEC [Parameters] |
Definition at line 143 of file risc_core.v.
I_DECFSZ [Parameters] |
Definition at line 143 of file risc_core.v.
I_INCF [Parameters] |
Definition at line 143 of file risc_core.v.
I_INCFSZ [Parameters] |
Definition at line 143 of file risc_core.v.
I_IORWF [Parameters] |
Definition at line 143 of file risc_core.v.
I_MOV [Parameters] |
Definition at line 143 of file risc_core.v.
I_MOVWF [Parameters] |
Definition at line 143 of file risc_core.v.
I_NOP [Parameters] |
Definition at line 143 of file risc_core.v.
I_RLF [Parameters] |
Definition at line 143 of file risc_core.v.
I_RRF [Parameters] |
Definition at line 143 of file risc_core.v.
I_SUBWF [Parameters] |
Definition at line 143 of file risc_core.v.
I_SWAPF [Parameters] |
Definition at line 143 of file risc_core.v.
I_XORWF [Parameters] |
Definition at line 143 of file risc_core.v.
I_BCF [Parameters] |
Definition at line 143 of file risc_core.v.
I_BSF [Parameters] |
Definition at line 143 of file risc_core.v.
I_BTFSC [Parameters] |
Definition at line 143 of file risc_core.v.
I_BTFSS [Parameters] |
Definition at line 143 of file risc_core.v.
I_ANDLW [Parameters] |
Definition at line 143 of file risc_core.v.
I_CALL [Parameters] |
Definition at line 143 of file risc_core.v.
I_CLRWDT [Parameters] |
Definition at line 143 of file risc_core.v.
I_GOTO [Parameters] |
Definition at line 143 of file risc_core.v.
I_IORLW [Parameters] |
Definition at line 143 of file risc_core.v.
I_MOVLW [Parameters] |
Definition at line 143 of file risc_core.v.
I_OPTION [Parameters] |
Definition at line 143 of file risc_core.v.
I_RETLW [Parameters] |
Definition at line 143 of file risc_core.v.
I_SLEEP [Parameters] |
Definition at line 143 of file risc_core.v.
I_TRIS [Parameters] |
Definition at line 143 of file risc_core.v.
I_XORLW [Parameters] |
Definition at line 143 of file risc_core.v.
INDF_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
TMR0_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
PCL_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
STAT_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
FSR_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
PORTA_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
PORTB_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
PORTC_ADDR [Parameters] |
Definition at line 182 of file risc_core.v.
K_SEL [Parameters] |
Definition at line 192 of file risc_core.v.
SFR_SEL [Parameters] |
Definition at line 192 of file risc_core.v.
RF_SEL [Parameters] |
Definition at line 192 of file risc_core.v.
STAT_WR_C [Parameters] |
Definition at line 197 of file risc_core.v.
STAT_WR_DC [Parameters] |
Definition at line 197 of file risc_core.v.
STAT_WR_Z [Parameters] |
Definition at line 197 of file risc_core.v.
rst [Registers] |
Definition at line 204 of file risc_core.v.
instr_0 [ 11 : 0 ] [Registers] |
Definition at line 205 of file risc_core.v.
instr_1 [ 11 : 0 ] [Registers] |
Definition at line 205 of file risc_core.v.
rst_r1 [Registers] |
Definition at line 206 of file risc_core.v.
rst_r2 [Registers] |
Definition at line 206 of file risc_core.v.
valid_1 [Registers] |
Definition at line 208 of file risc_core.v.
mask [ 7 : 0 ] [Registers] |
Definition at line 210 of file risc_core.v.
sfr_rd_data [ 7 : 0 ] [Registers] |
Definition at line 211 of file risc_core.v.
alu_op [ 3 : 0 ] [Registers] |
Definition at line 212 of file risc_core.v.
src1_sel [Registers] |
Definition at line 213 of file risc_core.v.
src1_sel_ [ 1 : 0 ] [Registers] |
Definition at line 214 of file risc_core.v.
stat_bwe [ 2 : 0 ] [Registers] |
Definition at line 219 of file risc_core.v.
pc_skz [Registers] |
Definition at line 222 of file risc_core.v.
pc_skz_ [Registers] |
Definition at line 222 of file risc_core.v.
pc_bset [Registers] |
Definition at line 223 of file risc_core.v.
pc_bset_ [Registers] |
Definition at line 223 of file risc_core.v.
pc_bclr [Registers] |
Definition at line 224 of file risc_core.v.
pc_bclr_ [Registers] |
Definition at line 224 of file risc_core.v.
pc_call [Registers] |
Definition at line 225 of file risc_core.v.
pc_call_ [Registers] |
Definition at line 225 of file risc_core.v.
pc_goto [Registers] |
Definition at line 226 of file risc_core.v.
pc_goto_ [Registers] |
Definition at line 226 of file risc_core.v.
pc_retlw [Registers] |
Definition at line 227 of file risc_core.v.
pc_retlw_ [Registers] |
Definition at line 227 of file risc_core.v.
invalidate_0 [Registers] |
Definition at line 231 of file risc_core.v.
w_we_ [Registers] |
Definition at line 234 of file risc_core.v.
rf_we_ [Registers] |
Definition at line 235 of file risc_core.v.
sfr_we_ [Registers] |
Definition at line 236 of file risc_core.v.
tris_we_ [Registers] |
Definition at line 237 of file risc_core.v.
w_we [Registers] |
Definition at line 240 of file risc_core.v.
rf_we1 [Registers] |
Definition at line 242 of file risc_core.v.
rf_we2 [Registers] |
Definition at line 242 of file risc_core.v.
rf_we3 [Registers] |
Definition at line 242 of file risc_core.v.
opt_we [Registers] |
Definition at line 244 of file risc_core.v.
trisa_we [Registers] |
Definition at line 245 of file risc_core.v.
trisb_we [Registers] |
Definition at line 246 of file risc_core.v.
trisc_we [Registers] |
Definition at line 247 of file risc_core.v.
tmr0_we [Registers] |
Definition at line 250 of file risc_core.v.
pc_we [Registers] |
Definition at line 252 of file risc_core.v.
stat_we [Registers] |
Definition at line 253 of file risc_core.v.
fsr_we [Registers] |
Definition at line 254 of file risc_core.v.
porta_we [Registers] |
Definition at line 255 of file risc_core.v.
portb_we [Registers] |
Definition at line 256 of file risc_core.v.
portc_we [Registers] |
Definition at line 257 of file risc_core.v.
wdt_clr [Registers] |
Definition at line 262 of file risc_core.v.
inst_addr [ 10 : 0 ] [Registers] |
Definition at line 275 of file risc_core.v.
pc [ 10 : 0 ] [Registers] |
Definition at line 276 of file risc_core.v.
pc_r [ 10 : 0 ] [Registers] |
Definition at line 280 of file risc_core.v.
pc_r2 [ 10 : 0 ] [Registers] |
Definition at line 280 of file risc_core.v.
w [ 7 : 0 ] [Registers] |
Definition at line 284 of file risc_core.v.
status [ 7 : 0 ] [Registers] |
Definition at line 285 of file risc_core.v.
fsr [ 6 : 0 ] [Registers] |
Definition at line 287 of file risc_core.v.
tmr0 [ 7 : 0 ] [Registers] |
Definition at line 289 of file risc_core.v.
option [ 5 : 0 ] [Registers] |
Definition at line 290 of file risc_core.v.
trisa [ 7 : 0 ] [Registers] |
Definition at line 293 of file risc_core.v.
trisb [ 7 : 0 ] [Registers] |
Definition at line 294 of file risc_core.v.
trisc [ 7 : 0 ] [Registers] |
Definition at line 295 of file risc_core.v.
porta_r [ 7 : 0 ] [Registers] |
Definition at line 298 of file risc_core.v.
portb_r [ 7 : 0 ] [Registers] |
Definition at line 299 of file risc_core.v.
portc_r [ 7 : 0 ] [Registers] |
Definition at line 300 of file risc_core.v.
portaout [ 7 : 0 ] [Registers] |
Definition at line 301 of file risc_core.v.
portbout [ 7 : 0 ] [Registers] |
Definition at line 302 of file risc_core.v.
portcout [ 7 : 0 ] [Registers] |
Definition at line 303 of file risc_core.v.
u0 register_file [Components] |
instd_zero [Registers] |
Definition at line 410 of file risc_core.v.
w_we1 [Registers] |
Definition at line 475 of file risc_core.v.
w_we1_ [Registers] |
Definition at line 475 of file risc_core.v.
u3 mux2_8 [Components] |
u4 alu [Components] |
u21 mux2_8 [Components] |
Definition at line 688 of file risc_core.v.
u31 mux2_7 [Components] |
Definition at line 696 of file risc_core.v.
u5 mux2_8 [Components] |
u6 mux2_8 [Components] |
Definition at line 751 of file risc_core.v.
u7 inc8 [Components] |
Definition at line 755 of file risc_core.v.
u8 presclr_wdt [Components] |
Definition at line 760 of file risc_core.v.
u9 mux2_11 [Components] |
Definition at line 816 of file risc_core.v.
u10 mux2_11 [Components] |
Definition at line 817 of file risc_core.v.
u11 mux2_11 [Components] |
Definition at line 818 of file risc_core.v.
u12 mux2_11 [Components] |
Definition at line 819 of file risc_core.v.
u13 inc11 [Components] |
Definition at line 822 of file risc_core.v.
invalidate_1_r1 [Registers] |
Definition at line 824 of file risc_core.v.
invalidate_1_r2 [Registers] |
Definition at line 824 of file risc_core.v.
u22 mux8_1 [Components] |
Definition at line 837 of file risc_core.v.
u14 sfifo4x11 [Components] |
Definition at line 839 of file risc_core.v.