register_file Module Reference

Inheritance diagram for register_file:

mrisc mrisc_top

List of all members.

Processes

ALWAYS_12  ( clk )
ALWAYS_13  ( clk )

Ports

clk 
rst 
rf_rd_bnk 
rf_rd_addr 
rf_rd_data 
rf_we 
rf_wr_bnk 
rf_wr_addr 
rf_wr_data 

Inputs

clk 
rst 
rf_rd_bnk [ 1 : 0 ]
rf_rd_addr [ 4 : 0 ]
rf_we 
rf_wr_bnk [ 1 : 0 ]
rf_wr_addr [ 4 : 0 ]
rf_wr_data [ 7 : 0 ]

Outputs

rf_rd_data [ 7 : 0 ]

Registers

wr_data_tmp  [ 7 : 0 ]
rd_wr_addr_equal 

Components

rf0 generic_dpram


Detailed Description

Definition at line 71 of file register_file.v.


Member Function Documentation

[Processes]
ALWAYS_12 ( clk )

Definition at line 103 of file register_file.v.

 
00103 always @(posedge clk)
00104         rd_wr_addr_equal <= #1 (rd_addr==wr_addr) & rf_we;
00105 
00106 assign

[Processes]
ALWAYS_13 ( clk )

Definition at line 108 of file register_file.v.

 
00108 always @(posedge clk)
00109         wr_data_tmp <= #1 rf_wr_data;
00110 
00111 // This is the actual Memory
00112 generic_dpram


Member Data Documentation

clk [Ports]

Definition at line 71 of file register_file.v.

rst [Ports]

Definition at line 71 of file register_file.v.

rf_rd_bnk [Ports]

Definition at line 72 of file register_file.v.

rf_rd_addr [Ports]

Definition at line 72 of file register_file.v.

rf_rd_data [Ports]

Definition at line 72 of file register_file.v.

rf_we [Ports]

Definition at line 73 of file register_file.v.

rf_wr_bnk [Ports]

Definition at line 73 of file register_file.v.

rf_wr_addr [Ports]

Definition at line 73 of file register_file.v.

rf_wr_data [Ports]

Definition at line 73 of file register_file.v.

clk [Inputs]

Definition at line 75 of file register_file.v.

rst [Inputs]

Definition at line 75 of file register_file.v.

rf_rd_bnk [ 1 : 0 ] [Inputs]

Definition at line 76 of file register_file.v.

rf_rd_addr [ 4 : 0 ] [Inputs]

Definition at line 77 of file register_file.v.

rf_rd_data [ 7 : 0 ] [Outputs]

Definition at line 78 of file register_file.v.

rf_we [Inputs]

Definition at line 79 of file register_file.v.

rf_wr_bnk [ 1 : 0 ] [Inputs]

Definition at line 80 of file register_file.v.

rf_wr_addr [ 4 : 0 ] [Inputs]

Definition at line 81 of file register_file.v.

rf_wr_data [ 7 : 0 ] [Inputs]

Definition at line 82 of file register_file.v.

wr_data_tmp [ 7 : 0 ] [Registers]

Definition at line 89 of file register_file.v.

rd_wr_addr_equal [Registers]

Definition at line 90 of file register_file.v.

rf0 generic_dpram [Components]

Definition at line 112 of file register_file.v.


The documentation for this class was generated from the following files:

Generated on Sat Apr 19 14:27:20 2008 by  doxygen 1.5.4-20071103