00001 ///////////////////////////////////////////////////////////////////// 00002 //// //// 00003 //// Mini-RISC-1 //// 00004 //// Register File //// 00005 //// //// 00006 //// //// 00007 //// Author: Rudolf Usselmann //// 00008 //// rudi@asics.ws //// 00009 //// //// 00010 //// //// 00011 //// D/L from: http://www.opencores.org/cores/minirisc/ //// 00012 //// //// 00013 ///////////////////////////////////////////////////////////////////// 00014 //// //// 00015 //// Copyright (C) 2000-2002 Rudolf Usselmann //// 00016 //// www.asics.ws //// 00017 //// rudi@asics.ws //// 00018 //// //// 00019 //// This source file may be used and distributed without //// 00020 //// restriction provided that this copyright statement is not //// 00021 //// removed from the file and that any derivative work contains //// 00022 //// the original copyright notice and the associated disclaimer.//// 00023 //// //// 00024 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 00025 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 00026 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 00027 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 00028 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 00029 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 00030 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 00031 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 00032 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 00033 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 00034 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 00035 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 00036 //// POSSIBILITY OF SUCH DAMAGE. //// 00037 //// //// 00038 ///////////////////////////////////////////////////////////////////// 00039 00040 // CVS Log 00041 // 00042 // $Id: register_file.v,v 1.3 2002/10/01 12:44:24 rudi Exp $ 00043 // 00044 // $Date: 2002/10/01 12:44:24 $ 00045 // $Revision: 1.3 $ 00046 // $Author: rudi $ 00047 // $Locker: $ 00048 // $State: Exp $ 00049 // 00050 // Change History: 00051 // $Log: register_file.v,v $ 00052 // Revision 1.3 2002/10/01 12:44:24 rudi 00053 // Tweaked code a bit - trying to get it run faster ... 00054 // 00055 // Revision 1.2 2002/09/27 15:35:40 rudi 00056 // Minor update to newer devices ... 00057 // 00058 // 00059 // 00060 // 00061 // 00062 // 00063 // 00064 // 00065 // 00066 // 00067 // 00068 00069 `timescale 1ns / 10ps 00070 00071 module register_file( clk, rst, 00072 rf_rd_bnk, rf_rd_addr, rf_rd_data, 00073 rf_we, rf_wr_bnk, rf_wr_addr, rf_wr_data); 00074 00075 input clk,rst; 00076 input [1:0] rf_rd_bnk; 00077 input [4:0] rf_rd_addr; 00078 output [7:0] rf_rd_data; 00079 input rf_we; 00080 input [1:0] rf_wr_bnk; 00081 input [4:0] rf_wr_addr; 00082 input [7:0] rf_wr_data; 00083 00084 wire clk; 00085 wire [7:0] rf_rd_data; 00086 wire [6:0] rd_addr; 00087 wire [6:0] wr_addr; 00088 wire [7:0] rf_rd_data_mem; 00089 reg [7:0] wr_data_tmp; 00090 reg rd_wr_addr_equal; 00091 00092 // Simple Read & Write Address Mapping to memory address 00093 assign rd_addr[6] = ~rf_rd_addr[4]; 00094 assign rd_addr[5:3] = rf_rd_addr[4] ? {rf_rd_bnk, rf_rd_addr[3]} : 3'h0; 00095 assign rd_addr[2:0] = rf_rd_addr[2:0]; 00096 00097 assign wr_addr[6] = ~rf_wr_addr[4]; 00098 assign wr_addr[5:3] = rf_wr_addr[4] ? {rf_wr_bnk, rf_wr_addr[3]} : 3'h0; 00099 assign wr_addr[2:0] = rf_wr_addr[2:0]; 00100 00101 // This logic is to bypass the register file if we are reading and 00102 // writing (in previous instruction) to the same register 00103 always @(posedge clk) 00104 rd_wr_addr_equal <= #1 (rd_addr==wr_addr) & rf_we; 00105 00106 assign rf_rd_data = rd_wr_addr_equal ? wr_data_tmp : rf_rd_data_mem; 00107 00108 always @(posedge clk) 00109 wr_data_tmp <= #1 rf_wr_data; 00110 00111 // This is the actual Memory 00112 generic_dpram #(7,8) rf0( 00113 .rclk( clk ), 00114 .rrst( rst ), 00115 .rce( 1'b1 ), 00116 .oe( 1'b1 ), 00117 .raddr( rd_addr ), 00118 .do( rf_rd_data_mem ), 00119 .wclk( clk ), 00120 .wrst( rst ), 00121 .wce( 1'b1 ), 00122 .we( rf_we ), 00123 .waddr( wr_addr ), 00124 .di( rf_wr_data ) 00125 ); 00126 00127 endmodule