Test Project
|
Entities | |
behv | architecture |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
std_logic_unsigned |
Generics | |
n | natural := 2 |
number of bits of counter |
Ports | |
Q | out std_logic_vector ( n - 1 downto 0 ) |
globals | |
clk | in std_logic |
control ports | |
clear | in std_logic |
clear counter | |
count | in std_logic |
outputs | |
valid | out std_logic |
valid |