TestDoxygen
1.0.21
Test for Doxygen
|
00001 00004 /* 00005 Created 110110 00006 MRU 110920 00007 110920 Moved HW definitions from SIMRCV.h 00008 110704 Added INIT_MAXSPI 00009 110110 Added character memory definitions 00010 110105 Added DIFFNDX 00011 110101 Corrected auto increment mode enable bit 00012 101229 Added macro MAX7456setbits(REG, BITS, MASK) 00013 MRU 101201 00014 101201 Added STAT definitions 00015 00016 */ 00017 #ifndef _MAX7456_H_ 00018 #define _MAX7456_H_ 00019 00020 #include <avr/io.h> 00021 #include <avr/pgmspace.h> 00022 #include "myportbits.h" 00023 00024 /* Only one of JR_DEFS, SVEN_DEFS and XMEGA_DEFS are defined */ 00025 #if (HARDWARE == SVEN_DEFS) 00026 /* No MAX7456 in Sven's HW */ 00027 #endif /* SVEN_DEFS */ 00028 00029 #if (HARDWARE == JR_DEFS) && (VTIDEVICE == MAX7456OSD) 00030 /* Port/pin definitions */ 00031 /* Composite video INT0/PD2 negative flank. We don't need the 00032 interrupt for MAX7456, but we do need to read HSYNC in the 00033 VSYNC ISR to see if it's an even or odd field 00034 */ 00035 #define CVPORT PORTD 00036 #define CVDDR DDRD 00037 #define CVPINR PIND 00038 #define CVPORTPIN PORTD2 00039 #define CVDD DDD2 00040 #define CVPIN PIND2 00041 00042 /* Vertical sync PB0, interrupt */ 00043 #define VSYNC_vect PCINT0_vect 00044 #define VSYNCPORT PORTB 00045 #define VSYNCDDR DDRB 00046 #define VSYNCPINR PINB 00047 #define VSYNCPORTPIN PORTB0 00048 #define VSYNCDD DDB0 00049 #define VSYNCPIN PINB0 00050 #define VSYNCIBIT PCINT0 00051 #define VSYNCMSKREG PCMSK0 /* Pin change mask register */ 00052 00053 #define INIT_MUXS0 /* No multiplexer for MAX7456 */ 00054 #define INIT_OE /* No odd/even pin for MAX7456 */ 00055 00056 /* MAX7456 definitions, this is for the prototype board, CS pin 00057 I/O is with the SPI pins 00058 */ 00059 #define MAXCSPORT PORTB 00060 #define MAXCSDDR DDRB 00061 #define MAXCSPINR PINB 00062 #define MAXCSPIN PB2 00063 /* INITMAX7456 does not set up the SPI, see INIT_MAXSPI below */ 00064 #define INITMAX7456 \ 00065 sbi(MAXCSDDR, MAXCSPIN); /* CS as output */ \ 00066 DESELMAX7456 /* deselect MAX7456 */ 00067 /* No CV interrupt */ 00068 #define ENBL_CVINT 00069 #define DSBL_CVINT 00070 00071 /* Initialise composite video, interrupt not needed */ 00072 #if (VTIDEVICE == MAX7456OSD) 00073 #define INIT_CV \ 00074 cbi(CVDDR, CVPIN); /* Set as input */ 00075 #endif 00076 00077 #define VSYNCINT_ON /* VSYNC interrupt on */ \ 00078 setbit(VSYNCMSKREG, VSYNCIBIT); /* Allow VSYNC pin int */ \ 00079 setbit(PCICR, PCIE0); /* enable PCINT 0 to 7 */ 00080 00081 #define VSYNCINT_OFF /* Disable VSYNC interrupt */ \ 00082 clrbit(VSYNCMSKREG, VSYNCIBIT); 00083 00084 /* Macro to initialise VSYNC HW */ 00085 #define INIT_VSYNC \ 00086 cbi(VSYNCDDR, VSYNCPIN); /* Set as input */ \ 00087 VSYNCINT_ON /* Enable interrupt */ 00088 00089 #endif /* JR_DEFS*/ 00090 00091 #if (HARDWARE == XMEGA_DEFS) 00092 /* Port/pin definitions */ 00093 #if (PGMFUNCTION == RECEIVER) 00094 00095 #endif /* RECEIVER */ 00096 00097 #if (PGMFUNCTION == SIMULATOR) 00098 00099 #endif /* SIMULATOR */ 00100 #endif /* XMEGA_DEFS*/ 00101 /* Lines in display */ 00102 #define NTSC_LINES 13 00103 #define PAL_LINES 16 00104 #define CHARSPERLN 30 /* Characters in a line */ 00105 /* size of array for MAXreadregs() */ 00106 #define REGCNT 10 00107 00109 enum WRREGADDR 00110 { VM0W, /* Video mode 0 */ 00111 VM1W, /* Video mode 1 */ 00112 HOSW, /* Horizontal offset */ 00113 VOSW, /* Vertical offset */ 00114 DMMW, /* Display memory mode */ 00115 DMAHW, /* Display Memory Address High */ 00116 DMALW, /* Display Memory Address Low */ 00117 DMDIW, /* Display Memory Data In */ 00118 CMMW, /* Character Memory Mode */ 00119 CMAHW, /* Character Memory Address High */ 00120 CMALW, /* Character Memory Address Low */ 00121 CMDIW, /* Character Memory Data In */ 00122 OSDMW, /* OSD Insertion Mux */ 00123 RB0W, /* Row 0 Brightness */ 00124 RB1W, /* Row 1 Brightness */ 00125 RB2W, /* Row 2 Brightness */ 00126 RB3W, /* Row 3 Brightness */ 00127 RB4W, /* Row 4 Brightness */ 00128 RB5W, /* Row 5 Brightness */ 00129 RB6W, /* Row 6 Brightness */ 00130 RB7W, /* Row 7 Brightness */ 00131 RB8W, /* Row 8 Brightness */ 00132 RB9W, /* Row 9 Brightness */ 00133 RB10W, /* Row 10 Brightness */ 00134 RB11W, /* Row 11 Brightness */ 00135 RB12W, /* Row 12 Brightness */ 00136 RB13W, /* Row 13 Brightness */ 00137 RB14W, /* Row 14 Brightness */ 00138 RB15W, /* Row 15 Brightness */ 00139 OSDBLW = 0x6C /* OSD Black Level */ 00140 }; 00144 #define READFLG 0x80 00145 enum RDREGADDR 00146 { VM0R = READFLG, /* Video mode 0 */ 00147 VM1R, /* Video mode 1 */ 00148 HOSR, /* Horizontal offset */ 00149 VOSR, /* Vertical offset */ 00150 DMMR, /* Display memory mode */ 00151 DMAHR, /* Display Memory Address High */ 00152 DMALR, /* Display Memory Address Low */ 00153 DMDIR, /* Display Memory Data In */ 00154 CMMR, /* Character Memory Mode */ 00155 CMAHR, /* Character Memory Address High */ 00156 CMALR, /* Character Memory Address Low */ 00157 CMDIR, /* Character Memory Data In */ 00158 OSDMR, /* OSD Insertion Mux */ 00159 RB0R, /* Row 0 Brightness */ 00160 RB1R, /* Row 1 Brightness */ 00161 RB2R, /* Row 2 Brightness */ 00162 RB3R, /* Row 3 Brightness */ 00163 RB4R, /* Row 4 Brightness */ 00164 RB5R, /* Row 5 Brightness */ 00165 RB6R, /* Row 6 Brightness */ 00166 RB7R, /* Row 7 Brightness */ 00167 RB8R, /* Row 8 Brightness */ 00168 RB9R, /* Row 9 Brightness */ 00169 RB10R, /* Row 10 Brightness */ 00170 RB11R, /* Row 11 Brightness */ 00171 RB12R, /* Row 12 Brightness */ 00172 RB13R, /* Row 13 Brightness */ 00173 RB14R, /* Row 14 Brightness */ 00174 RB15R, /* Row 15 Brightness, 0x9F */ 00175 OSDBLR = 0xEC, /* OSD Black Level */ 00176 STATR = 0xA0, /* Status, read only */ 00177 DMDOR = 0xB0, /* Display Memory Data Out, read only */ 00178 CMDOR = 0xC0 /* Character Memory Data Out, read only */ 00179 }; 00180 /* All arguments must be uint8_t */ 00181 #define SETVAR(var, mask, val) \ 00182 (((uint8_t) var & ~(uint8_t) mask) | ((uint8_t) val & (uint8_t) mask)) 00183 /* Register definitions from datasheet */ 00185 #define VM0VSSMSK ((uint8_t) 0x40) 00186 #define VSSNTSC ((uint8_t) 0x00) /* NTSC */ 00187 #define VSSPAL ((uint8_t) 0x40) /* PAL */ 00188 #define VM0SSMMSK ((uint8_t) 0x30) 00189 #define SSMAUTO ((uint8_t) 0x00) /* Select sync mode auto */ 00190 #define SSMEXT ((uint8_t) 0x20) /* Select sync mode external */ 00191 #define SSMINT ((uint8_t) 0x30) /* Select sync mode internal */ 00192 #define VM0DSPMSK ((uint8_t) 0x08) 00193 #define DSPOFF ((uint8_t) 0x00) /* OSD display off */ 00194 #define DSPON ((uint8_t) 0x08) /* OSD display on */ 00195 #define VM0VSMSK ((uint8_t) 0x04) 00196 #define VSIMM ((uint8_t) 0x00) /* VSYNC immediate */ 00197 #define VSNXT ((uint8_t) 0x04) /* VSYNC on next VSYNC input */ 00198 #define SWRESET ((uint8_t) 0x02) /* Software reset */ 00199 #define VM0VBNMSK ((uint8_t) 0x01) 00200 #define DSPENB ((uint8_t) 0x00) /* Display enable */ 00201 #define DSPDIS ((uint8_t) 0x01) /* Display disable */ 00202 00204 #define VM1BCKMSK ((uint8_t) 0x80) /* Background mode */ 00205 #define BCKLOCAL ((uint8_t) 0x00) /* default set by DMM[5], DMD[7] */ 00206 #define BCKGREY ((uint8_t) 0x80) /* Grey background */ 00207 #define VM1BKMMSK ((uint8_t) 0x70) /* Background bright mode */ 00208 #define BKM00 ((uint8_t) 0x00) /* 0% */ 00209 #define BKM07 ((uint8_t) 0x10) /* 7% */ 00210 #define BKM14 ((uint8_t) 0x02) /* 14% */ 00211 #define BKM21 ((uint8_t) 0x30) /* 21% */ 00212 #define BKM28 ((uint8_t) 0x40) /* 28% default */ 00213 #define BKM35 ((uint8_t) 0x50) /* 35% */ 00214 #define BKM42 ((uint8_t) 0x60) /* 42% */ 00215 #define BKM49 ((uint8_t) 0x70) /* 49% */ 00216 #define VM1BLKMSK ((uint8_t) 0x0C) /* Blink time mask, BT */ 00217 #define BLINK2 ((uint8_t) 0x00) /* 2 fields */ 00218 #define BLINK4 ((uint8_t) 0x04) /* default 4 fields */ 00219 #define BLINK6 ((uint8_t) 0x08) /* 6 fields */ 00220 #define BLINK8 ((uint8_t) 0x0C) /* 8 fields */ 00221 #define VM1DTYMSK ((uint8_t) 0x03) /* Blink duty cycle */ 00222 #define DUTY11 ((uint8_t) 0x00) /* Duty cycle 1:1 BT */ 00223 #define DUTY12 ((uint8_t) 0x01) /* Duty cycle 1:2 BT */ 00224 #define DUTY13 ((uint8_t) 0x02) /* Duty cycle 1:3 BT */ 00225 #define DUTY31 ((uint8_t) 0x03) /* default Duty cycle 3:1 BT */ 00226 00228 #define HOSMASK ((uint8_t) 0x3F) /* Bits 7,6 not used */ 00229 #define HOSLEFT ((uint8_t) 0x00) /* 32 pixels to left */ 00230 #define HOSMID ((uint8_t) 0x20) /* default 0 pixels offset */ 00231 #define HOSRIGHT ((uint8_t) 0x3F) /* 31 pixels to right */ 00232 00234 #define VOSMASK ((uint8_t) 0x1F) /* Bits 7,6 not used */ 00235 #define VOSLEFT ((uint8_t) 0x00) /* 16 pixels up */ 00236 #define VOSMID ((uint8_t) 0x10) /* default 0 pixels offset */ 00237 #define VOSRIGHT ((uint8_t) 0x1F) /* 15 pixels down */ 00238 00240 #define DMMOPMMASK ((uint8_t) 0x40) /* Op mode mask */ 00241 #define OPM16 ((uint8_t) 0x00) /* 16 bit mode, default */ 00242 #define OPM8 ((uint8_t) 0x40) /* 8 bit mode */ 00243 #define DMMLBCMASK ((uint8_t) 0x20) /* local background control, 16 bit */ 00244 #define LBCVIN ((uint8_t) 0x00) /* Video IN if external sync, def */ 00245 #define LBCBKM ((uint8_t) 0x20) /* set to background */ 00246 #define DMMBLKMASK ((uint8_t) 0x10) /* Blink control, 16 bit */ 00247 #define BLKOFF ((uint8_t) 0x00) /* blink off, default */ 00248 #define BLKON ((uint8_t) 0x10) /* blink on */ 00249 #define DMMINVMASK ((uint8_t) 0x08) /* Invert pixel mask, 16 bit mode */ 00250 #define DMMATTRMSK (DMMLBCMASK | DMMBLKMASK | DMMINVMASK) /* Attributes */ 00251 #define INVOFF ((uint8_t) 0x00) /* chars are white, default */ 00252 #define INVON ((uint8_t) 0x08) /* chars are black */ 00253 #define DMMCLDMASK ((uint8_t) 0x04) /* Clear display memory */ 00254 #define CLDOFF ((uint8_t) 0x00) /* Normal mode, don't clear, def */ 00255 #define CLDON ((uint8_t) 0x04) /* Clear display memory */ 00256 #define DMMVSCMASK ((uint8_t) 0x02) /* Vertical sync clear */ 00257 #define VSCIMDT ((uint8_t) 0x00) /* def, clear dsp memory if CLDON */ 00258 #define VSCNEXT ((uint8_t) 0x02) /* clear dsp memory on next VSYNC */ 00259 #define DMMAIMMASK ((uint8_t) 0x01) /* Auto-increment mode */ 00260 #define AIMDSBL ((uint8_t) 0x00) /* def. Auto increment disable */ 00261 #define AIMENBL ((uint8_t) 0x01) /* Auto increment enable */ 00262 #define AIMEND ((uint8_t) 0xFF) /* end auto increment write */ 00263 00265 #define DMAHBSBMASK ((uint8_t) 0x02) /* Byte selection bit */ 00266 #define BSBCHAR ((uint8_t) 0x00) /* DMAH[1], DMAL is character addr */ 00267 #define BSBATTR ((uint8_t) 0x02) /* DMAH[1], DMAL is attribute addr */ 00268 #define DMABIT8MSK ((uint8_t) 0x01) /* Character memory addr bit 8 */ 00269 00271 #define CMALBYTMASK ((uint8_t) 0x3F /* Byte address for four pixels */ 00272 00273 /* Character attributes */ 00274 00276 #define STATRSTMSK ((uint8_t) 0x40) 00277 #define RESETBUSY ((uint8_t) 0x40) /* not finished reset */ 00278 #define RESETRDY ((uint8_t) 0x00) /* Reset finished */ 00279 #define STATCMSMSK ((uint8_t) 0x20) /* Character memory status */ 00280 #define CMSAVAIL ((uint8_t) 0x00) /* CMS available */ 00281 #define CMSUNAVAIL ((uint8_t) 0x20) /* CMS unavailable */ 00282 00283 #define STATLOSMSK ((uint8_t) 0x04) /* Loss of sync */ 00284 #define LOSINSYNC ((uint8_t) 0x00) /* Sync'sd with video in */ 00285 #define LOSNOSYNC ((uint8_t) 0x04) /* Not sync'd with video in */ 00286 #define STATNTSCMSK ((uint8_t) 0x02) /* NTSC bit */ 00287 #define NTSCOFF ((uint8_t) 0x00) /* No NTSC detected */ 00288 #define NTSCON ((uint8_t) 0x02) /* NTSC detected */ 00289 #define STATPALMSK ((uint8_t) 0x01) /* PAL bit */ 00290 #define PALOFF ((uint8_t) 0x00) /* No PAL detected */ 00291 #define PALON ((uint8_t) 0x01) /* PAL detected */ 00292 00294 #define OSDBLBLCMSK ((uint8_t) 0x10) /* Automatic black level */ 00295 #define BLCON ((uint8_t) 0x00) /* Black level control on */ 00296 #define BLCOFF ((uint8_t) 0x10) /* Black level control off */ 00297 /* Do not change bits 0-3, they are factory set */ 00298 00300 #define SELMAX7456 cbi(MAXCSPORT, MAXCSPIN); 00301 #define DESELMAX7456 sbi(MAXCSPORT, MAXCSPIN); 00302 00303 /* VSYNC_FLANK value is POS_FLANK if pin VSYNCPIN of port VSYNCPORT has value 1, 00304 otherwise NEG_FLANK 00305 */ 00306 #define VSYNC_FLANK PC_FLANK(VSYNCPINR, VSYNCPIN) 00307 00308 /* Line numbers in display, these can change for NTSC. The text 00309 lines in the display must be spaced by at least FONTLINES scanlines 00310 PAL has 576 visible lines, NTSC has 486 (odd + even field) 00311 Fix the headline, info1 and info2 lines as adjacent lines at the top, 00312 Move the time line to the last line 00313 For SW OSD the line number is where the top line appears 00314 Avoid lines near thetop for the time being, need some time to build 00315 the texts after the VSYNC 00316 */ 00318 enum PALLINENOS {PALHEADLN = 1, PALINFO1LN = 13, 00319 PALINFO2LN = 14, PALTIMELN = 15, PALSPARELN = 2}; 00321 enum NTSCLINENOS {NTSCHEADLN = 1, NTSCINFO1LN = 10, 00322 NTSCINFO2LN = 11, NTSCTIMELN = 12, NTSCSPARELN = 2}; 00323 /* DIFFNDX is the index into dsplines for which the line number 00324 is different in NTSC and PAL, used in HW_OSD.c 00325 */ 00326 #define DIFFNDX TIMNDX 00327 /* 16 lines for PAL, 13 for NTSC */ 00328 00329 /* Some definitions for reading and writing character memory 00330 Number of bytes for pixels in one character */ 00331 #define CMBYTES 54 00332 /* array for storing pixel data */ 00333 typedef uint8_t CMpixels[CMBYTES]; 00334 00336 #define BLACKPIXEL 0x00 00337 #define WHITEPIXEL 0x02 00338 #define TRNGRAYPIXEL 0x01 /* Transparent (ext sync), grey (int) */ 00339 /* Positions of the pixels in byte, left shift count */ 00340 #define LEFTPIXEL 6 /* left pixel */ 00341 #define LMIDPIXEL 4 /* left middle */ 00342 #define RMIDPIXEL 2 /* right middle */ 00343 #define RGHTPIXEL 0 /* right pixel */ 00344 #define PIXELMASK 0x03 /* mask for pixel value */ 00345 /* Commands for NVM read/write */ 00346 #define READNVM 0x50 /* read NVM into shadow memory */ 00347 #define WRITENVM 0xA0 /* write shadow memory to NVM */ 00348 00349 /* Macros */ 00350 /* INIT_MAXSPI sets up the SPCR and SPSR registers for the MAX7456 00351 These may be different from those of the DOGM display, so it must 00352 be executed at every read and write, and NOT be interrupted 00353 */ 00354 #define INIT_MAXSPI \ 00355 /* Enable SPI, master, CPOL = CPHA = 0, MSB first, Fosc/4 */ \ 00356 SPCR = (1 << SPE) | (1 << MSTR); \ 00357 SPSR = 0; /* Single speed */ 00358 00365 #define MAX7456setbits(REG, BITS, MASK) \ 00366 MAX7456write_byte(REG ## W, \ 00367 (MAX7456read_byte(REG ## R) & ~MASK) | (BITS & MASK)) 00368 00369 /* Function definitions */ 00370 00371 uint8_t MAX7456read_byte(uint8_t regaddr); 00372 unsigned int MAX7456rdCA_CATR(uint8_t regaddr); 00373 void MAX7456write_byte(uint8_t val, uint8_t regaddr); 00374 void MAX7456_init(void); 00375 void MAX7456_ClearDisplay(); 00376 void MAX7456dsptext( 00377 char *text, /* null terminated string, max CHARSPERLN */ 00378 PGM_P transtab, /* ASCII to MAX7456 CA translation table */ 00379 int8_t attributes, /* attributes, 0 if none */ 00380 int8_t line, /* Line number 0-12 (NTSC), 0-15 (PAL) */ 00381 int8_t column); /* column number, 0 CHARSPERLN - 1 (29) */ 00382 void MAXreadregs(uint8_t *regs); 00383 void MAX7456readCM(uint8_t CA, CMpixels *pixels); 00384 #endif /* _MAX7456_H_ */