00001 /**************************************************************************//** 00002 * \file adc_Cfg.h 00003 * 00004 * \brief This file provides all the configurations provided by ADC module 00005 * of Freescale MPC563 power-pc MCU 00006 * 00007 * \version 1.0A - Initial Draft 00008 * \date 25 June 2010 00009 * 00010 * \version 1.1A - Design changed to support run-time CCW addition and 00011 * configuration 00012 * \date 16 July 2010 00013 *****************************************************************************/ 00014 #ifndef ADC_CFG_H 00015 #define ADC_CFG_H 00016 /****************************************************************************** 00017 Include Files 00018 ******************************************************************************/ 00019 00020 /****************************************************************************** 00021 Type defines 00022 ******************************************************************************/ 00023 00024 /*************************************************************************** 00025 ************* QADCMCR - Module Configuration Register settings ************* 00026 ****************************************************************************/ 00027 /** \defgroup QADCMCR_REG_SETTINGS QADCMCR register settings */ /*@{*/ 00028 /** \brief This macro defines the value for disabling the ADC stop mode */ 00029 #define ADC_DISABLE_STOP_MODE 0 00030 /** \brief This macro defines the value for enabling the ADC stop mode */ 00031 #define ADC_ENABLE_STOP_MODE 1 00032 00033 /** \brief This macro defines the value for ignoring the freeze commands 00034 provided in CCWs */ 00035 #define ADC_IGNORE_FREEZE 0 00036 /** \brief This macro defines the value for enabling the freeze commands 00037 provided in CCWs */ 00038 #define ADC_ENABLE_FREEZE 1 00039 00040 /** \brief This macro defines the value for locking the ADC mode of operation. 00041 This prevents accidental change in mode of operation */ 00042 #define ADC_MODE_LOCK_ENABLE 0 00043 /** \brief This macro defines the value for unlocking the ADC mode of operation. 00044 This will enable change in mode of operation */ 00045 #define ADC_MODE_LOCK_DISABLE 1 00046 00047 /*@}*/ 00048 00049 /*************************************************************************** 00050 ******************** QADCINT - Interrupt Register ************************** 00051 ****************************************************************************/ 00052 /** \defgroup QADCINT_REG_SETTINGS QADCINT register settings */ /*@{*/ 00053 /** \brief This macro used to develop the QADCINT reg value by grouping all 00054 the different field values */ 00055 #define ADC_INT_PRIO(Q1Prio,Q2Prio) ((((U16)(Q2Prio)) << 5) | (Q1Prio)) 00056 /*@}*/ 00057 00058 /*************************************************************************** 00059 ****************************** QACR1 - Control Reg-1 *********************** 00060 ****************************************************************************/ 00061 /** \defgroup QACR1_REG_SETTINGS QACR1 register settings */ /*@{*/ 00062 /* Queue-1 Completion interrupt enable */ 00063 /** \brief This macro used to disable completion interrupt for Queue-1 */ 00064 #define ADC_Q1_COMP_INT_DISABLE 0 00065 /** \brief This macro used to enable completion interrupt for Queue-1 */ 00066 #define ADC_Q1_COMP_INT_ENABLE 1 00067 00068 /* Queue-1 Pause interrupt enable */ 00069 /** \brief This macro used to disable pause interrupt for Queue-1 */ 00070 #define ADC_Q1_PAUSE_INT_DISABLE 0 00071 /** \brief This macro used to enable pause interrupt for Queue-1 */ 00072 #define ADC_Q1_PAUSE_INT_ENABLE 1 00073 00074 /*@}*/ 00075 /*************************************************************************** 00076 ******************************** QACR2 - Control Reg-2 ********************* 00077 ****************************************************************************/ 00078 /** \defgroup QACR2_REG_SETTINGS QACR2 register settings */ /*@{*/ 00079 /* Queue-2 Completion interrupt enable */ 00080 /** \brief This macro used to disable completion interrupt for Queue-2 */ 00081 #define ADC_Q2_COMP_INT_DISABLE 0 00082 /** \brief This macro used to enable completion interrupt for Queue-2 */ 00083 #define ADC_Q2_COMP_INT_ENABLE 1 00084 00085 /* Queue-2 Pause interrupt enable */ 00086 /** \brief This macro used to disable pause interrupt for Queue-2 */ 00087 #define ADC_Q2_PAUSE_INT_DISABLE 0 00088 /** \brief This macro used to enable pause interrupt for Queue-2 */ 00089 #define ADC_Q2_PAUSE_INT_ENABLE 1 00090 00091 /*@}*/ 00092 00093 /** \brief This macro defines the total no.of CCWs available in 00094 each ADC converter module */ 00095 #define ADC_TOT_CCW 64 00096 00097 /** \brief This defines the address for the ADC converter module A register 00098 group */ 00099 #define QADC_MOD_A (( struct QADC64_tag *) (INTERNAL_MEMORY_BASE + 0x304800)) 00100 /** \brief This defines the address for the ADC converter module B register 00101 group */ 00102 #define QADC_MOD_B (( struct QADC64_tag *) (INTERNAL_MEMORY_BASE + 0x304C00)) 00103 00104 #endif